Low Power Pulse-Triggered Flip-Flops Designs with Hybrid Logic Style
碩士 === 國立雲林科技大學 === 電子與資訊工程研究所 === 99 === In recent years, power consumption is important issue on System on Chip and Very Large Scale Integration design. Besides the portable electronic products are indispensable on our life so that low-power IC design technique becomes a major trend. The clock sys...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/04631727021339755036 |