DESIGN OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS
碩士 === 大同大學 === 電機工程學系(所) === 99 === In this thesis, we design an all-digital phase-locked loop (ADPLL) circuit in which resolution in the frequency detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The ADPLL generates output clock frequency with on...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09055301273166765638 |