A 8-BIT 1GS/s TWO-STEP ADC WITHOUT SAMPLE AND HOLD CIRCUIT
碩士 === 大同大學 === 電機工程學系(所) === 99 === My thesis describes the implementation of a 8-bit 1G sample/s two-step ADC with a delay line circuit, level shifter and a transfer table, but without sample and hold circuits. This architecture is design to improve the sample rate of the traditional two-step ADC....
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/02528740499854454583 |