Optimization Algorithm Applied to Zero Skew Clock Tree Implementation

碩士 === 淡江大學 === 電機工程學系碩士班 === 99 === In this paper in the system on chip design, we propose a method to determine a nonlinear branch connection location in the timing pulse wiring design that is 1) based on Fitted Elmore Delay model and it then combines 2) the evolution characteristics of the Partic...

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Bibliographic Details
Main Authors: Chih-Chung Lin, 林志忠
Other Authors: 李揚漢
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/22584086746554152375
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Summary:碩士 === 淡江大學 === 電機工程學系碩士班 === 99 === In this paper in the system on chip design, we propose a method to determine a nonlinear branch connection location in the timing pulse wiring design that is 1) based on Fitted Elmore Delay model and it then combines 2) the evolution characteristics of the Particle Swarm Optimization (PSO) algorithm to change the connection topology of timing pulse wiring from H shape to X shape; it determine and finds, under the requirement of Zero Clock Skew, the best branch location in the X shape wiring. With this design it can effectively reduce the total required wire length of the timing pulse wiring and reduce the overall timing pulse delay. We propose the methodology of ‘Optimization Algorithm Applied to Zero Skew Clock Tree Implementation’ and from many test experiments under the requirement of Zero Clock Skew it reveals that our proposed design algorithm, comparing with the conventional λ-Geometry DME routing method, can effectively reduce the total wiring length of the timing pulse wiring by 5% ~ 19% and clock delay by 14%~-22% ; consequently it appears that our proposed algorithm by changing the conventional H shape into X shape in the wiring design is a realizable and effective design methodology.