| Summary: | 碩士 === 淡江大學 === 電機工程學系碩士班 === 99 === Arithmetic logic unit and multiplier for the CPU core component, responsible for all operations, the central processor is one of power consumption components to reduce power consumption of this two parts, can reduce CPU power consumption.
Pipeline structure is a common way used in high-speed operation. In the synchronous system, there are two problems Clock network will bring a lot of power consumption and clock skew causes Solve the wrong logic value. There is a different circuit needs to be designed to solve the synchronization system The two major problems. Therefore synchronization system is converted into Asynchronous system. In the asynchronous system In the clock network is to replace the handshake circuit in order to manage the operation of the pipeline.
In this paper, we apply the TSMC 0.35 to simulate the multiplier core components: use of a robust system of non-synchronous handshaking structure. To design 16 * 16-bit asynchronous pipelined multiplier for distributed systems to improve computing speed, Booth multipliers, and pipeline systems approach to achieve this non-synchronous distributed multiplier.
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