The Design of 16x16 bit Booth Multiplier with Asynchronous Pipeline Technique
碩士 === 淡江大學 === 電機工程學系碩士班 === 99 === Arithmetic logic unit and multiplier for the CPU core component, responsible for all operations, the central processor is one of power consumption components to reduce power consumption of this two parts, can reduce CPU power consumption. Pipeline structure...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/33595884756579039407 |