Realize multilevel-floorplanning for VLSI using sequence pair
碩士 === 國立臺北科技大學 === 電機工程系所 === 99 === In the traditional IC design flow, the result of floorplanning will affect the IC’s area, wirelength, and other electrical characteristics. Small area equals to low cost and short wirelength means better performace, so floorplanning problem is very important in...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/v8a99k |