Automatic Layout Generator for Low Power Asynchronous Circuits
碩士 === 南台科技大學 === 電子工程系 === 99 === A layout generator can produce optimized circuit layouts for taping out IC chips, which is a reasonable and desirable EDA tool for every VLSI circuit designer. However, such tool never seen in the market since producing a full-chip layout implementation is an extre...
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| Format: | Others |
| Language: | zh-TW |
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| Online Access: | http://ndltd.ncl.edu.tw/handle/46852941297684731671 |