Designing Self-timed Adders Using Low Power/Cost Differential Logic

• Main Authors: Pei-Hsuan YU, 余姵萱
• Other Authors: Jung-Lin YANG
• Format: Others
• Language: zh-TW
• Online Access: http://ndltd.ncl.edu.tw/handle/98859762504894300582

碩士 === 南台科技大學 === 電子工程系 === 99 === Abstract We know that the global financial crisis of 2008 had gone through its worst period of time, and the semiconductor industry is getting recovered from the past year. How EDA and VLSI design engineers seize the moment of chances in the industry is the most critical issue. Also, many data show that global warming is elevated in trend, so we need to do something to help the earth as part of the global community. Thus, this thesis proposed a low-power/cost-variant asynchronous circuit design structure on self-timed adder, and to prove that this self-timed adder is advantageous as verified by researches and work cited in many technical reports, for example low-power dissipation, low eletro-magenetic interference, easy-to-modulation, no clock skew, and so on. Nonetheless, the difficulty of the circuit design is greater than the synchronous counterpart, and lacking of matured EDA tools, the asynchronous circuit is therefore rarely being used in the applications of electronic system for varied kinds. We hope to use lower power to simulate the DCVSL circuit sample by implementing a self-timed adder with parameters to be analyzed: area, delay time, and performance of power dissipation. The performance of circuit sample may be applied to the design of the asynchronous design, so the electronic design engineers could use self-timed circuit to develop low-power and high performance of electronic system. We hope that the circuit sample and the performance analysis in this thesis would provide a way of asynchronous design methodology to assist electronic system engineers to develop self-timed circuits. The architecture of the pseudo DCVSL circuit sample is applicable for the development of the self-timed datapath element. Based on this architecture, the self-timed circuit has gone through partial post-simulation and measurement analysis to prove it is actually better than conventional dual-rail design; whose area is 28% lesser, power dissipation is 22% economical, and the speed is 25% faster. The feature of the sample circuit is the more complex the circuit implementation is, the more improvement on the performance it may arise. Thus, this circuit sample is showing an outperformed result. Keys: Dual-rail, asynchronous, self-timed, adder, low-power