A Study of nLDMOS Parameters Optimization in Latch-Up Prevention by Taguchi Method

• Main Authors: Tzung-Shian Wu, 吳宗賢
• Other Authors: Shen-Li Chen
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/91390330070180788578

碩士 === 國立聯合大學 === 電子工程學系碩士班 === 99 === For invented electronic products to change with each passing day, and semiconductor process progress day after day. The ESD(electrostatic discharge) problem will be serious with semiconductor scaling. HBM(Human Body Model) and CDM(Charge Device Model) issues are very critical as the channel length and gate-oxide thickness reduced. In the high voltage applications, there are many kind of ESD protection techniques in high voltage device. Latch-Up immunity of HV devices is not good as comparied with low voltage process devices. Latch-Up effect will be degraded the integral circuit reliability under HV operation voltage. In this thesis, Chapter-1 introduces HV device applications；Chapter-2 make a description about HV device development, device structure and related testing theorem；A experiment method and HV nLDMOS device simulations will be discussed in Chapter-3 and 4, respectively. The Chapter-5 is a conclusion. The TSMC 0.6um 40V/5V process technology is used to design a low trigger voltage and high holding voltage of an nLDMOS in this thesis, which are the drain side N-type adaptive layer, source side P-type adaptive layer and N+ buried layer technologies. A modified polysilicon length overlap field oxide to control trigger voltage and holding voltage, so that it can be operated in the 40V HV nLDMOS applications. Eventually, the Taguchi method method is used to evaluated a HV device, and which compared with a single variable modified experimental mehod, and it is expected that this method can reduce experimental cost and consume time.