High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories

碩士 === 國立臺灣科技大學 === 電機工程系 === 99 === High-speed testing techniques and yield enhancement techniques for content-addressable memories are proposed in this thesis. According to the fault effects of the widely used fault models for CAM arrays, the fault models can be categorized into two types-serial t...

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Main Authors: Han-yu Hsu, 許涵喻
Other Authors: Shyue-Kung Lu
Format: Others
Language:en_US
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/9r7smy
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spelling ndltd-TW-099NTUS54421432019-05-15T20:42:06Z http://ndltd.ncl.edu.tw/handle/9r7smy High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories 內容定址記憶體之高速測試與良率提昇技術 Han-yu Hsu 許涵喻 碩士 國立臺灣科技大學 電機工程系 99 High-speed testing techniques and yield enhancement techniques for content-addressable memories are proposed in this thesis. According to the fault effects of the widely used fault models for CAM arrays, the fault models can be categorized into two types-serial testable faults (STFs) and parallel testable faults (PTFs). For PTFs (e.g., stuck-mismatched faults), all CAM columns can be tested in a parallel manner. Alternatively, STFs can only be tested sequentially column by column. Therefore the test time is dominated by STFs. This situation is getting worse if the number of columns increases. To cure this dilemma, the CAM array is first partitioned into b row banks and a steering module is added for each row block. The steering module switches between the parallel test mode (for PTFs) and the serial test mode (for STFs). Therefore, b STFs can be tested at the same time. This will greatly decrease the overall test time. For the proposed techniques, the BIST circuit can be shared by b row banks. Therefore, the area of the BIST area will be minimized. As the density and capacity of CAMs increase, it is more prone to suffer from defects. Therefore, the fabrication yield will be very low. It is inevitable to seek for efficient fault-tolerance techniques for improving the yield of CAMs. In this thesis, instead of replacing faulty cells with an entire CAM word as used in the conventional techniques, the block-based approach is presented. Redundant columns are not added here for simplicity. According to simulation results, the hardware overhead is 1.31% for a 1024 × 1024-bit CAM array. We also compare the repair rates and reliabilities of our approach with previous fault-tolerant techniques. It is also found that our approach outperforms their results. Shyue-Kung Lu 呂學坤 2011 學位論文 ; thesis 68 en_US
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description 碩士 === 國立臺灣科技大學 === 電機工程系 === 99 === High-speed testing techniques and yield enhancement techniques for content-addressable memories are proposed in this thesis. According to the fault effects of the widely used fault models for CAM arrays, the fault models can be categorized into two types-serial testable faults (STFs) and parallel testable faults (PTFs). For PTFs (e.g., stuck-mismatched faults), all CAM columns can be tested in a parallel manner. Alternatively, STFs can only be tested sequentially column by column. Therefore the test time is dominated by STFs. This situation is getting worse if the number of columns increases. To cure this dilemma, the CAM array is first partitioned into b row banks and a steering module is added for each row block. The steering module switches between the parallel test mode (for PTFs) and the serial test mode (for STFs). Therefore, b STFs can be tested at the same time. This will greatly decrease the overall test time. For the proposed techniques, the BIST circuit can be shared by b row banks. Therefore, the area of the BIST area will be minimized. As the density and capacity of CAMs increase, it is more prone to suffer from defects. Therefore, the fabrication yield will be very low. It is inevitable to seek for efficient fault-tolerance techniques for improving the yield of CAMs. In this thesis, instead of replacing faulty cells with an entire CAM word as used in the conventional techniques, the block-based approach is presented. Redundant columns are not added here for simplicity. According to simulation results, the hardware overhead is 1.31% for a 1024 × 1024-bit CAM array. We also compare the repair rates and reliabilities of our approach with previous fault-tolerant techniques. It is also found that our approach outperforms their results.
author2 Shyue-Kung Lu
author_facet Shyue-Kung Lu
Han-yu Hsu
許涵喻
author Han-yu Hsu
許涵喻
spellingShingle Han-yu Hsu
許涵喻
High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories
author_sort Han-yu Hsu
title High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories
title_short High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories
title_full High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories
title_fullStr High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories
title_full_unstemmed High-speed Testing and Yield Enhancement Techniques for Content-addressable Memories
title_sort high-speed testing and yield enhancement techniques for content-addressable memories
publishDate 2011
url http://ndltd.ncl.edu.tw/handle/9r7smy
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