A DC-DC Converter with Capacitor Multiplier Technique to Reduce the Compensation Capacitor
碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === This thesis aims to realize a capacitor multiplier technique to reduce the compensation capacitor of a DC-DC converter. To reduce the huge compacitor of the traditional DC-DC converter, a new architecture named “dual-loop control mode” is used. In this thesis, th...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/g54gr5 |