| Summary: | 碩士 === 國立臺灣大學 === 電信工程學研究所 === 99 === In present generation, high-frequency and high-speed phase-lock-loop plays an important role in wireline or wireless communication systems. However, high frequency PLL has considerable difficulty in realization. Thus, it has become a popular topic in the IEEE journals and conferences. In this thesis, a variety of PLLs has been proposed and fabricated in CMOS technology. The first step of implementation of the PLL is to accomplish a VCO and high-frequency divider chain, which is the most difficult part of high speed PLL. Once the VCO and high-frequency divider chain has been proven and measured correctly, the rest parts of the PLL such as PFD, CP, loop-filter, and static dividers will be fulfilled in my next work in chapter 3, and then the phase-lock-loop is complete. By using TSMC CMOS 0.18μm process, this thesis has proposed a 24-GHz PLL front-end circuit design, and an ultra low-power 24-GHz Phase-Lock-Loop for collision avoidance radar system. In those works, we widely use a wide range of transformer feedback voltage control oscillator, achieving lower power consumption issue and better phase noise and higher output power. And using the cascade divider to achieve the current re-use to minimize the power consumption.
The first chapter describes the general use of the basic phase-lock-loop device characteristics and design features. In chapter 2, a 24-GHz transformer feedback VCO and divider chain opened a prelude to making 24-GHz PLL, consuming DC power of 45mW and the measured phase noise is -93dBc/Hz @ 1-MHz. Later on, gathering previous experience of circuits implementation, the 24-GHz PLL front-end has been modified and accomplish into an ultra low-power PLL in chapter 3, consuming DC power of 29.8mW, ultra low phase noise: -122dBc/Hz @ 10-MHz and wide tuning range of 20.8-23.37-GHz.
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