Design and Implementation of Low Power CMOS RF Phase-Lock-Loop with Cascoded Divider
碩士 === 國立臺灣大學 === 電信工程學研究所 === 99 === In present generation, high-frequency and high-speed phase-lock-loop plays an important role in wireline or wireless communication systems. However, high frequency PLL has considerable difficulty in realization. Thus, it has become a popular topic in the IEEE...
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| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/90743846728105077714 |