The Bipolar/MOS SPICE Model Approach for Analyzing 40nm PD SOI NMOS Device Considering Floating-Body Effect

• Main Authors: Shang-Wei Fang, 方上維
• Other Authors: 郭正邦
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/72788362760183981640

碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === The thesis reports modeling the 40nm PD SOI NMOS device considering floating-body effect via Bipolar/MOS SPICE model approach. Chapter 1 gives a brief introduction about SOI CMOS devices and the scaling trends, including the comparison of the difference between the PD SOI and the FD SOI CMOS devices. Chapter 2 describes the current conduction mechanism of the PD SOI MOS and the compact model constructed from Bipolar/MOS SPICE model approach. As verified by experimentally measured data and 2D simulation results, the compact model of the PD SOI NMOS provides an accurate prediction under DC condition. Chapter 3 discusses the ac model of the PD SOI MOS devices considering the floating body effect for transient analysis. From the study, during the turn-on transient, the current gain of the parasitic bipolar transistor becomes larger as the longer rise time of the gate voltage. As verified by 2D simulation results, the compact SOI model gives an accurate prediction of transient behavior. Chapter 4 is conclusion and future work.