Compact Test Pattern Selection for Small Delay Defect

• Main Authors: Chia-Yuan Chang, 張家源
• Other Authors: Chien-Mo Li
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/91803745070286953546

碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === Testing for small delay defect (SDD) is necessary for ensuring product quality in modern nanometer technologies. Existing commercial tools such as transition fault Automatic Test Pattern Generation (ATPG) tools and timing-aware ATPG tools are either inefficient in detecting SDD or suffering from large CPU time and pattern count. Therefore, this thesis proposes an algorithm that selects a small number of test patterns for small delay defects from a large N-detect test set. This algorithm uses static upper and lower bound analysis to quickly estimate the sensitized path length so the CPU time can be reduced in pattern selection process. By ignoring easy faults, only a partial fault dictionary, instead of a complete fault dictionary, is built for test pattern selection. Experimental results show that, with very similar quality, the selected test set is 32% smaller than that of timing-aware ATPG. With the proposed selection algorithm, SDD test sets are no longer too expensive to apply.