Implementation and Analysis of Speculative Flow Control for On-chip Interconnection Network
碩士 === 國立清華大學 === 電機工程學系 === 99 === Flow control mechanism controls buffer usage for packet transmitting from node to node. Speculative flow control has been proposed in [2]. First, we design and implement this flow control mechanism by Verilog HDL. We build up a buffered crosspoint network with spe...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/80810694416262524747 |