Rigorous Design, Modeling and Analysis of High-Frequency VLSI Clock Trees
碩士 === 國立清華大學 === 電機工程學系 === 99 === Clock signal is the most important part in synchronous circuit and a good circuit design must have a robust clock signal. Clock skew and clock jitter are the most critical factors whether the design meets the specifications or not. Therefore, many devote to inven...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34437908692015147703 |