Investigation of Charge Trapping Characteristic and Reliability Issues for High-k/Metal gate MOSFETs

• Main Authors: Jou-Miao Shih, 施柔妙
• Other Authors: Ting-Chang Chang
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/73320578482266040514

碩士 === 國立中山大學 === 物理學系研究所 === 99 === Electronic devices such as high power devices, microprocessors and memories in integrated circuit are primarily composed of metal-oxide-semiconductor field effect transistors (MOSFETs), due to the advantages of low cost, low power consumption and easy to scale down. However, the aggressively scaled conventional MOS devices have suffered remarkable short channel effects such as drain induced barrier lowering, punch-through, and direct-tunneling gate leakage. These problems not only lower the gate controllability but also increase the standby power consumption. Because the SiO2 dielectric and poly-gate are improper for CMOS application below 45 nm technology node due to the critical gate leakage current. Therefore, we investigate the electrical characteristics and physical mechanisms of MOSFETs with HfO2/TixN1-x gate stacks by using split C-V, pulsed Id-Vg, and charge-pumping techniques. The experimental results indicate that dynamic stress is more serious than static stress, and hot-carrier effect corresponding to different gate stress biases demonstrate distinct dominant degradation behaviors and the charge-trapping phenomenon. Furthermore, different concentration of titanium in TiN metal gate significantly affect device characteristics associated with the amount of nitrogen diffusion from the metal gate to high-k bulk and the SiO2/Si interface layer.