| Summary: | 碩士 === 國立東華大學 === 電機工程學系 === 99 === The process technique of two dimensional (2D) chip is problematic because the transistor count increases rapidly on the chip. Overly long latency and excessive power consumption are two difficult problems. To improve the defects, emerging 3D integrated circuit (IC) technique can improve the disadvantage of 2D IC. The 3D IC concept optimizes application of the NoC architecture and there are many studying results show the performance of 3D NoC is better than 2D NoC such as spite of power, latency. Hence, the design of 3D NoC architecture becomes important issue.
This paper uses the packet header partition to construct the three dimensional (3D) switch for different larged-sized 3D NoC architectures. Application of the method to create the 3D switch for 8*8*4 3D NoC architectures with 256 coordinates shows that the 3D switch efficiently screens input packets and determines the packet arbitration for the 7 input ports. The proposed 3D switch is used in the 3D NoC and compared with 2D NoC. Then, using the experiment results to evaluate performance for the 3D NoC and 2D NoC, the performance of the 3D NoC for the power and the delay are better than 2D NoC.
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