Switch Architecture Design for 3D Networks-on-Chip Application
碩士 === 國立東華大學 === 電機工程學系 === 99 === The process technique of two dimensional (2D) chip is problematic because the transistor count increases rapidly on the chip. Overly long latency and excessive power consumption are two difficult problems. To improve the defects, emerging 3D integrated circuit...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/19152833459286237151 |