寬範圍低功率消耗頻率倍乘器之延遲鎖定迴路
碩士 === 國立彰化師範大學 === 電子工程學系 === 99 === The proposed wide range low power frequency multiplier is based on a delay locked loop circuit. Delay locked loop circuit and start-up control circuit are used to provide a wide input frequency range. There is no harmonic locking problem in the operating frequen...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94195619106727476358 |
| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 99 === The proposed wide range low power frequency multiplier is based on a delay locked loop circuit. Delay locked loop circuit and start-up control circuit are used to provide a wide input frequency range. There is no harmonic locking problem in the operating frequency range. The output frequency range of the proposed frequency multiplier is from 90 MHz to 604 MHz. The TSMC 0.35μm 2P4M CMOS process parameters are used to simulate the delay locked loop based frequency multiplier circuit, and the power supply voltage is 3.3 V. The simulation results show that the power consumption of frequency multiplier when output frequency at 90 MHz is 2.47 mW, and when output frequency at 604 MHz is 3.33 mW, respectively.
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