寬範圍低功率消耗頻率倍乘器之延遲鎖定迴路
碩士 === 國立彰化師範大學 === 電子工程學系 === 99 === The proposed wide range low power frequency multiplier is based on a delay locked loop circuit. Delay locked loop circuit and start-up control circuit are used to provide a wide input frequency range. There is no harmonic locking problem in the operating frequen...
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| Format: | Others |
| Language: | zh-TW |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94195619106727476358 |