A 500 MS/s Flash-ADC with Selectable Power Consumption
碩士 === 國立彰化師範大學 === 積體電路設計研究所 === 99 === In this thesis, a 500M sample/s Flash-ADC is presented which can select 6 different power consumption from 6 different input Vbias. In comparator, we have 6 different input Vbias to obtain 6 different resolution and power consumption. In this study, we use T...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/52655116055866746727 |