An 1.25-GHz All Digital Phase-Locked Loop for Low Supply Voltage Applications
碩士 === 國立中央大學 === 電機工程研究所 === 99 === This thesis presents an 1.25-GHz 8-phase all digital phase-locked loop (ADPLL) for low supply voltage applications. The ADPLL uses multistage sub-feedback loop and ring-based delay line (RB-DL) in the proposed multiphase digital controlled oscillator (MP-DCO) to...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/79754856578837473535 |