The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride

碩士 === 國立交通大學 === 電子物理系所 === 99 === We analyze the trap states and establish the electron transport model for SONOS memories with embedded Si-NCs in Si3N4. Initially, the distributions of Si-SiO2 interface state density (Dit) under different growth conditions are obtained by capacitance-voltage (C-V...

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Main Authors: Ho, Chi-Ying, 何紀瑩
Other Authors: Chen, Jenn-Fang
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/92585393274739196468
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description 碩士 === 國立交通大學 === 電子物理系所 === 99 === We analyze the trap states and establish the electron transport model for SONOS memories with embedded Si-NCs in Si3N4. Initially, the distributions of Si-SiO2 interface state density (Dit) under different growth conditions are obtained by capacitance-voltage (C-V) measurements and deep-level transient spectroscopy (DLTS) measurements with the aid of C-V simulations. The interface traps and near-interfacial oxide traps close to Si-SiO2 interface were observed in all samples. When scaling down the tunnel oxide thickness, a corresponding increase of charge loss is observed due to leakage current induced by interface traps. Therefore, the analysis of interface states is essential for the understanding of charge loss mechanism. We utilize high-low frequency C-V method and DLTS measurement to extract the distributions of the interface state density in the Si band gap (EgSi). According to these results, various fabrication processes can cause different distribution of interface trap states. The samples with N2O–grown tunnel oxide have the lowest interface state densities, which is attributed to the formation of more strong Si-N bonds in N2O-grown tunnel oxide layer. For the thick tunnel oxide layer, the interface traps are significantly reduced, and thus the leakage current can be effectively suppressed. In addition, we also elucidate the influence of Si-NCs deposition conditions on the interface state density. The process of Si-NCs formation can reduce the interface state density, which is attributed to the annihilation of Si dangling bonds by residual hydrogen-atom in Si-NCs formation. Next, we establish the electron transport model for the structures with different tunnel oxide thicknesses. In DLTS measurements, the Si-NCs related signals are observed at all Si-NCs_2 min samples. For the thick tunnel oxide layer, the activation energies of the Si-NCs related traps are larger than others, suggesting a different electron transport process for the thick tunnel oxide layer. Thus, the electron transport mechanism is related to different tunnel oxide thicknesses. According to the band diagram simulation of SONOS with Si-NCs, the electron emission time constants of various mechanisms (direct-tunneling, thermionic, and trap-to-trap tunneling) were calculated. Consequently, we propose two electron transport paths for Si-NCs related signals with different tunnel oxide thicknesses. For 2.5 nm tunnel oxide samples, electrons are thermally activated from Si-NCs related states to nitride bulk traps (ETD), and then tunnel into the SiO2/Si interface states. For 3.0 nm tunnel oxide samples, electrons are thermally activated from Si-NCs related states to nitride bulk traps (ETD), and then are thermally activated from ETD to other nitride bulk traps (ETA), followed by a direct tunneling into the Si conduction band. For thick tunnel oxide samples, the tunneling probability between ETD and SiO2/Si interface states is extremely low, and thus the electron transport path is dominated by thermal activation process from ETD to ETA, resulting in longer electron emission times for Si-NCs related states. These results also indicate that the 3.0 nm tunnel oxide samples have longer retention time than others, which are consistent with the retention measurement results. We also utilize the retention measurement with applied gate bias to investigate the retention ability of Si-NCs related states. In these measurements, we can obtain the time constant for charge loss of our samples. The obtained time constants of charge loss are consistent with the electron emission time obtained from Si-NCs related states in DLTS measurements. Thus, charge storage in the Si-NCs related states is confirmed. Furthermore, the time constants of charge loss are also in good agreement with the simulation results by utilizing the electron transport model we established. These results can confirm our electron transport model, and also reveal that the formation of Si-NCs actually contribute to charge storage and improve device retention ability.
author2 Chen, Jenn-Fang
author_facet Chen, Jenn-Fang
Ho, Chi-Ying
何紀瑩
author Ho, Chi-Ying
何紀瑩
spellingShingle Ho, Chi-Ying
何紀瑩
The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride
author_sort Ho, Chi-Ying
title The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride
title_short The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride
title_full The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride
title_fullStr The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride
title_full_unstemmed The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride
title_sort trap analysis and establishment of electron transport model for sonos memory with embedded silicon nanocrystals in nitride
publishDate 2011
url http://ndltd.ncl.edu.tw/handle/92585393274739196468
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spelling ndltd-TW-099NCTU54290302015-10-13T20:37:25Z http://ndltd.ncl.edu.tw/handle/92585393274739196468 The trap analysis and establishment of electron transport model for SONOS memory with embedded silicon nanocrystals in nitride 氮化矽層內嵌奈米矽晶體之SONOS型記憶體的缺陷分析與電子傳輸機制研究 Ho, Chi-Ying 何紀瑩 碩士 國立交通大學 電子物理系所 99 We analyze the trap states and establish the electron transport model for SONOS memories with embedded Si-NCs in Si3N4. Initially, the distributions of Si-SiO2 interface state density (Dit) under different growth conditions are obtained by capacitance-voltage (C-V) measurements and deep-level transient spectroscopy (DLTS) measurements with the aid of C-V simulations. The interface traps and near-interfacial oxide traps close to Si-SiO2 interface were observed in all samples. When scaling down the tunnel oxide thickness, a corresponding increase of charge loss is observed due to leakage current induced by interface traps. Therefore, the analysis of interface states is essential for the understanding of charge loss mechanism. We utilize high-low frequency C-V method and DLTS measurement to extract the distributions of the interface state density in the Si band gap (EgSi). According to these results, various fabrication processes can cause different distribution of interface trap states. The samples with N2O–grown tunnel oxide have the lowest interface state densities, which is attributed to the formation of more strong Si-N bonds in N2O-grown tunnel oxide layer. For the thick tunnel oxide layer, the interface traps are significantly reduced, and thus the leakage current can be effectively suppressed. In addition, we also elucidate the influence of Si-NCs deposition conditions on the interface state density. The process of Si-NCs formation can reduce the interface state density, which is attributed to the annihilation of Si dangling bonds by residual hydrogen-atom in Si-NCs formation. Next, we establish the electron transport model for the structures with different tunnel oxide thicknesses. In DLTS measurements, the Si-NCs related signals are observed at all Si-NCs_2 min samples. For the thick tunnel oxide layer, the activation energies of the Si-NCs related traps are larger than others, suggesting a different electron transport process for the thick tunnel oxide layer. Thus, the electron transport mechanism is related to different tunnel oxide thicknesses. According to the band diagram simulation of SONOS with Si-NCs, the electron emission time constants of various mechanisms (direct-tunneling, thermionic, and trap-to-trap tunneling) were calculated. Consequently, we propose two electron transport paths for Si-NCs related signals with different tunnel oxide thicknesses. For 2.5 nm tunnel oxide samples, electrons are thermally activated from Si-NCs related states to nitride bulk traps (ETD), and then tunnel into the SiO2/Si interface states. For 3.0 nm tunnel oxide samples, electrons are thermally activated from Si-NCs related states to nitride bulk traps (ETD), and then are thermally activated from ETD to other nitride bulk traps (ETA), followed by a direct tunneling into the Si conduction band. For thick tunnel oxide samples, the tunneling probability between ETD and SiO2/Si interface states is extremely low, and thus the electron transport path is dominated by thermal activation process from ETD to ETA, resulting in longer electron emission times for Si-NCs related states. These results also indicate that the 3.0 nm tunnel oxide samples have longer retention time than others, which are consistent with the retention measurement results. We also utilize the retention measurement with applied gate bias to investigate the retention ability of Si-NCs related states. In these measurements, we can obtain the time constant for charge loss of our samples. The obtained time constants of charge loss are consistent with the electron emission time obtained from Si-NCs related states in DLTS measurements. Thus, charge storage in the Si-NCs related states is confirmed. Furthermore, the time constants of charge loss are also in good agreement with the simulation results by utilizing the electron transport model we established. These results can confirm our electron transport model, and also reveal that the formation of Si-NCs actually contribute to charge storage and improve device retention ability. Chen, Jenn-Fang 陳振芳 2011 學位論文 ; thesis 67 zh-TW