Studies of Exploratory Silicon Device Fabrication and Sensor Application

• Main Author: 陳豪育
• Other Authors: 簡昭欣
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/11988333361350713646

博士 === 國立交通大學 === 電子研究所 === 99 === In the past decade, SOI CMOSFETs have become attractive because they provide full dielectric isolation and reduced junction capacitance for high-performance circuit. Very recently, remarkable progress has been achieved in fully-depleted silicon on insulator (FD-SOI) technology. However, to maintain sufficient control of the short-channel effects (SCE), the body thickness has to be reduced to less than one-third of the gate length, thus introducing another difficulty on the variation control of the devices. In the second chapter, a new SOI device scheme featuring thin buried oxide (TBO-SOI) was investigated. The TBO-SOI scheme alleviates the Si thickness reduction requirement for shorter channel. It eases the process variation effects on the characteristics of the devices as well as the parasitic resistance impact due to reduction in the Si thickness. Furthermore, this SOI technology is able to combine both the benefit of an SOI and bulk device without additional complicated process. The superior SCE with a bulk-device-like body effect characteristic makes this device scheme more convincing than the ultra-thin Si SOI. Beyond the planar SOI, nanowire is the most compelling device channel architecture for complementary metal-oxide semiconductor (CMOS) device scaling towards 10 nm. The 2009 ITRS projected that gate lengths below 16 nm will be launched before 2015. From the perspective of the device gate length scalability, the nanowire channel with multiple-gate structure is expected to be the prospective candidate due to its superior gate control ability. More broadly, not only for the logic operation such as metal-oxide-semiconductor field-effect transistor (MOSFET), application of such a tiny semiconductor device for biomolecules sensing is evolving due to their similar dimensions. Thus, in the third chapter, we introduced three novel poly-Si nanowire field-effect transistor (NW FET) pH sensors fabrication using the conventional CMOS process. The nanowire width was scaled to sub-40 nm without requiring expensive lithography equipment. The surface ionic coupling operation of the buried-channel field-effect sensor exhibited superior pH sensitivity (threshold voltage shift > 100 mV/pH), which was beyond the Nernst limitation. The DNA detection capability and built-in memory functionality of NW FET enable interdisciplinary integration in very-large-scale integration (VLSI) circuits. The simple nanowire fabrication approaches realized manufacturing of uniform nanowire devices on a VLSI circuit, which provides a high sensitivity, compact, and cost-efficient biosensor systems-on-a-chip application. Although optical lithography has been a key driver for semiconductor development, meeting the resolution requirements for continued shrinkage in the technology roadmap is making it difficult to use traditional optical imaging systems when the wavelength of the light source must be reduced. Unlike increasing the exposure tool numerical aperture (NA) to fulfill the resolution requirement, change of a light source to the ultraviolet region demands development of its relative component, such as optics system and photoresist. Thus, extreme ultraviolet (EUV) lithography is a possible solution to the 16-nm node lithography, but its mask set price (extrapolated from 45- to 32-nm nodes) of up to 3 million US dollars is punitive for testing chips and pilot productions in the 16-nm era. E-beam lithography, a maskless process, is a highly attractive lithography alternative—at least in the initial circuit-verification stage. Nevertheless, recent experimental results revealed that e-beam lithography still suffered from line-width roughness and proximity effects when preparing high-density patterns. The unwanted secondary electron scattering increases the extent of chemical reactions in the photoresist, which results in the loss of resolution for adjacent features. In this chapter, we introduced a novel maskless and photoresist-free technology, which we named as “Nano Injection Lithography” (NInL) that prepared fine patterns for highly integrated devices. The application of NInL is to deposit pattern-transferred materials on the substrate surface directly through electron beam assisted chemical reactions to form the resulting pattern as etching hard mask for subsequent anisotropic etch. In the past decade, the electron beam assisted chemical reactions were used to define nanometer-scale structures having tiny pitches of periodic gratings, but not for the fabrication of MOSFETs. Herein, we reported the fabrication of a 6T-SRAM cell having an area of 0.039 ?慆2, by using the NInL. This lithography technique disclosed a new way to explore low-volume and high-value 16-nm CMOS device and circuit design with minimal additional investment, and obtained early access to extreme CMOS scaling. Finally, an attractive approach to form the exquisite metallic junction for ultra-scaled device was reported. The formation of a uniform, high tensile stress and low interfacial resistance nickel silicide (NiSi) on a 90-nm nMOSFET by introducing pulsed laser annealing (PLA) was investigated. This annealing approach eases NiSi phase transformation to NiSi2 through sufficient annealing temperatures using a low thermal budget laser irradiation, and introduces increased silicide tensile stress and a 0.2-eV reduction in Schottky barrier height (SBH). This NiSi2 layer has a superior film morphology at the silicon interface and avoids {111} NiSi2 facet induced junction leakage for shallow junction devices. By optimizing the laser energy, an 8 % nMOSFET Ion-Ioff enhancement was achieved, when compared with a conventional two-step rapid thermal annealing (RTA) process because of strain enhancement and interfacial resistance reduction.