| Summary: | 博士 === 國立交通大學 === 電子研究所 === 99 === The semiconductor VLSI technology is so successful that the transistor feature size and cost have been reduced exponentially with time since 1970s. Meanwhile, the transistor performance has increased constantly in the past decades and is expected to improve in the foreseeable future. The modern VLSI technology deeply relies on mechanical strain engineering, equivalent-oxide-thickness (EOT) reduction, ultra-shallow-junction (USJ) formation, and channel structure design for the purpose of boosting transistor performance and maintaining reasonable electrostatic characteristics of the short-channel transistors. In this dissertation we discussed and proposed novel methods to improve the aforementioned key process modules in an integration-friendly and cost-effective manner.
At first, a novel source/drain parasitic series resistance (Rsd) extraction method was proposed on the basis of carrier mobility universality. The merit of the method stems from the specifically arranged bias conditions in which the channel carrier mobility remains constant for high vertical electric fields. Rsd can be extracted using simple DC I-V measurements on a single test transistor without requiring information such as gate-oxide thickness, physical gate length, or effective channel length. It is this unique property which makes this method suitable for short-channel transistors. This method was verified with extensive experimental data and then utilized to evaluate the efficacy of the propose processes in the following chapters.
A novel millisecond-annealing-assisted fully-silicide (MSA-assisted FUSI) gate formation was discussed for the first time. This unique technique utilized an MSA for nickel silicide phase transformation, leading to a highly tensile FUSI gate electrode that exerts compressive stress in the channel region. Great selectivity of FUSI-gate formation was realized by implanting nitrogen in the area where FUSI-gate was to be prevented. The proposed integration scheme is highly cost-effective as compared with the conventional FUSI-gate process, which may need chemical-mechanical-polish (CMP), polysilicon recess, and extra lithography mask layers. Significant improvement in p-type transistor
driving current was thereby achieved resulting from enhanced hole mobility and the elimination of polysilicon depletion effect. Uniform FUSI-gate formation across various transistor dimensions was achieved with gate electrode feature size down to 30nm.
A novel process was proposed to modulate the distance, or proximity, between the tip of embedded silicon-germanium (e-SiGe) and the channel
region in pMOSFETs. Traditionally, sophisticated etching treatment was adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this dissertation, an extremely close proximity was achieved using self-aligned silicon-reflow (SASR) in hydrogen ambient. As opposed to the conventional approaches which had e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge as corroborated by transmission-electron-microscopy (TEM) analysis. Significant improvement in pMOSFET performance was also measured.
Enlarging gate voltage overdrive headroom is crucial to low-Vdd operation for nano-scale MOSFETs. We defined a new index, “Vth_lin-Vth_gm“, in order to describe the on-off transition abruptness in addition to the conventionally used index, sub-threshold swing. This new index is increasingly important to the advanced nano-scale MOSFETs for low-Vdd and low-Vth operation because it comprises an increasing portion of gate voltage consumed before turn-on. By introducing a novel USJ ion implantation (I/I) technique with reduced halo I/I dose, enhanced transistor performance and low Vdd-sensitivity were achieved because of quick on-off transition and improved carrier mobility.
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