Protection Design against Charged-Device-Model ESD Events in CMOS Integrated Circuits
碩士 === 國立交通大學 === 電子研究所 === 99 === With the nanoscale of CMOS processes, the devices in the integrated circuits (ICs) have been fabricated with very thin gate oxide to achieve high-speed and low- power consumption. But, electrostatic discharge (ESD) events were not scaled down with nanoscale CMOS te...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/92751057554505665821 |