White Space Distribution and Thermal-Aware 3D IC Placement
碩士 === 國立交通大學 === 電子研究所 === 99 === The 3D IC technologies can improve circuit performance and reduce wirelength. However, its thermal problems have become more serious. In this thesis, we propose a thermal aware 3D IC placement by using 3D partition to reduce the number of through-silicon via and to...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/20717950360207806785 |
| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 99 === The 3D IC technologies can improve circuit performance and reduce wirelength. However, its thermal problems have become more serious. In this thesis, we propose a thermal aware 3D IC placement by using 3D partition to reduce the number of through-silicon via and to optimize wirelength and temperature. In our methods, thermal effect is integrated with the placement process by net weighting so that the min-cut in every partition process would reduce temperature. Furthermore, we distribute white space uniformly to dissipate heat. The experimental results show that our thermal aware 3D IC placement algorithm can reduce about 29% max temperature with only 2% increase on wirelength.
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