Turbo Decoder with Parallel Architecture and Contention-Free Interleaver

• Main Authors: Wong, Cheng-Chi, 翁政吉
• Other Authors: Chang, Hsie-Chia
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/26347910110023998827

博士 === 國立交通大學 === 電子研究所 === 99 === This dissertation investigates the turbo decoders with parallel architecture and contention-free interleaver in pursuit of high throughput with reasonable cost. The benefits and disadvantages of conventional parallel schemes are examined; then the essential factors for throughput calculation are determined. Our discussions put emphasis on using multiple soft-in soft-out (SISO) decoders for single codeword. In addition to increasing the parallelism, the hybrid of parallel schemes is further applied for more speedup. However, the methodology leads to considerable complexity and inefficiency of processor. To reduce the complexity, we develop the multi-stage networks for the parallel data transmission in the turbo decoder. Two different types of apparatus are proposed for the designs using inter-block permutation (IBP) interleaver and quadratic permutation polynomial (QPP) interleaver, respectively. They can alleviate the routing congestion in the parallel design. To overcome the other difficulty, the processing schedule must be modified. We propose two different strategies to remove the data dependency and set their corresponding highefficiency schedules. One of them is aimed for general application, whereas the other is designed for specific case. The inactive periods within the decoding flow are greatly shortened in these schedules. Hence, the efficiency of the SISO decoder can increase. Four implemented works are presented in this dissertation. The multi-stage interconnection for IBP interleavers is applied to the first two parallel turbo decoders. Both the two designs contain multiple SISO decoders, each of which can process two or more symbols per cycle. One of them operates with the general high-efficiency schedule, and its idle time is completely removed. The third design exploits another interconnection for QPP interleavers. With such apparatus and appropriate control flow, it can use at most 8 SISO decoders to decodes all codeword blocks defined in the 3rd Generation Partnership Project Long Term Evolution standard. The remaining design also adopts QPP interleavers and the multi-stage network. It has higher parallelism than the other designs; moreover, its support of specific high-efficiency schedule results in the best efficiency. This design can achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations. The implementation results reveal that the proposed methods work successfully in the parallel architecture and raise the throughput significantly.