A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture

碩士 === 國立中興大學 === 電機工程學系所 === 99 === This thesis a single-ended input, Binary-weighted Capacitor Architecture SAR ADC using 0.18μm Mixed-Signal 1P6M process, to 909KHz Smple / s of the sampling frequency. Paper records a total of two wafermeasurement records, performance is best measured at a freque...

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Bibliographic Details
Main Authors:	Zhi-Xun Liu, 劉智勛
Other Authors:	林維亮
Format:	Others
Language:	zh-TW
Published:	2011
Online Access:	http://ndltd.ncl.edu.tw/handle/33696364586971597428

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spelling	ndltd-TW-099NCHU54410312017-10-29T04:34:05Z http://ndltd.ncl.edu.tw/handle/33696364586971597428 A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture 十位元單端輸入之連續逼近暫存式類比數位轉換器使用加權二進位電容結構 Zhi-Xun Liu 劉智勛碩士國立中興大學電機工程學系所 99 This thesis a single-ended input, Binary-weighted Capacitor Architecture SAR ADC using 0.18μm Mixed-Signal 1P6M process, to 909KHz Smple / s of the sampling frequency. Paper records a total of two wafermeasurement records, performance is best measured at a frequency of 90KHz input signal measured ENOB = 8.62bit, INL =- 2.7524LSB ~ 4.5413LSB, DNL =- 1LSB ~ 4.8605LSB. To separate digital and analog power source, the attempt to use deep Nwell for the substrate noise isolation, to reduce the noise impact of the single-ended architecture. In addition, the DAC capacitor array layout for a four-quadrantsymmetry . For the PCB of the inductance measurement method hasnot previously received aapproach, this is the "series" approach, and one set of voltage sources to complete the measurement. 林維亮 2011 學位論文 ; thesis 99 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立中興大學 === 電機工程學系所 === 99 === This thesis a single-ended input, Binary-weighted Capacitor Architecture SAR ADC using 0.18μm Mixed-Signal 1P6M process, to 909KHz Smple / s of the sampling frequency. Paper records a total of two wafermeasurement records, performance is best measured at a frequency of 90KHz input signal measured ENOB = 8.62bit, INL =- 2.7524LSB ~ 4.5413LSB, DNL =- 1LSB ~ 4.8605LSB. To separate digital and analog power source, the attempt to use deep Nwell for the substrate noise isolation, to reduce the noise impact of the single-ended architecture. In addition, the DAC capacitor array layout for a four-quadrantsymmetry . For the PCB of the inductance measurement method hasnot previously received aapproach, this is the "series" approach, and one set of voltage sources to complete the measurement.
author2	林維亮
author_facet	林維亮 Zhi-Xun Liu 劉智勛
author	Zhi-Xun Liu 劉智勛
spellingShingle	Zhi-Xun Liu 劉智勛 A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
author_sort	Zhi-Xun Liu
title	A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
title_short	A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
title_full	A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
title_fullStr	A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
title_full_unstemmed	A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
title_sort	10-bit single end successive approximation register adc with binary-weighted capacitor architecture
publishDate	2011
url	http://ndltd.ncl.edu.tw/handle/33696364586971597428
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A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture

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