A 10-bit Single End Successive Approximation Register ADC With Binary-weighted Capacitor Architecture
碩士 === 國立中興大學 === 電機工程學系所 === 99 === This thesis a single-ended input, Binary-weighted Capacitor Architecture SAR ADC using 0.18μm Mixed-Signal 1P6M process, to 909KHz Smple / s of the sampling frequency. Paper records a total of two wafermeasurement records, performance is best measured at a freque...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33696364586971597428 |