| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 99 === This thesis a single-ended input, Binary-weighted Capacitor Architecture SAR ADC using 0.18μm Mixed-Signal 1P6M process, to 909KHz Smple / s of the sampling frequency. Paper records a total of two wafermeasurement records, performance is best measured at a frequency of 90KHz input signal measured ENOB = 8.62bit, INL =- 2.7524LSB ~ 4.5413LSB, DNL =- 1LSB ~ 4.8605LSB.
To separate digital and analog power source, the attempt to use deep Nwell for the substrate noise isolation, to reduce the noise impact of the single-ended architecture. In addition, the DAC capacitor array layout for a four-quadrantsymmetry . For the PCB of the inductance measurement method hasnot previously received aapproach, this is the "series" approach, and one set of voltage sources to complete the measurement.
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