An Enhancing Reliability Method for Multilevel Flash Memory by Using Interleaving Arrangement
碩士 === 國立中興大學 === 資訊科學與工程學系所 === 99 === In this work, we propose a new interleaving arrangement to average the temporary error bits caused by dichotomic serial sensing architecture in multilevel flash. Furthermore, the proposed arrangement also can effectively enhance the reliability (MTBF) of multi...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/44622038307594636418 |
| Summary: | 碩士 === 國立中興大學 === 資訊科學與工程學系所 === 99 === In this work, we propose a new interleaving arrangement to average the temporary error bits caused by dichotomic serial sensing architecture in multilevel flash. Furthermore, the proposed arrangement also can effectively enhance the reliability (MTBF) of multilevel flash. In our experiment results, interleaving arrangement can provide low error bits rate then only using bit-layer arrangement. And use simple switch circuits realization interleaving arrangement. In bit-layer method, using dichotomic serial sensing output stage will create cell spare part lengths uneven demand.
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