Electroless Deposition of Barrier and Seed Layersof Through Silicon Via
碩士 === 國立中興大學 === 化學工程學系所 === 99 === The development of science is constantly progressing. The densification of electronic components continuously increases. In order to meet this general demand, many new three-dimensional (3D) electronic packaging technologies are now emerging, especially with th...
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ndltd-TW-099NCHU50630102017-10-29T04:34:04Z http://ndltd.ncl.edu.tw/handle/00998999624929322458 Electroless Deposition of Barrier and Seed Layersof Through Silicon Via 以無電鍍法沉積矽通孔之阻障層與導電層 Chia-Pei Chou 周嘉珮 碩士 國立中興大學 化學工程學系所 99 The development of science is constantly progressing. The densification of electronic components continuously increases. In order to meet this general demand, many new three-dimensional (3D) electronic packaging technologies are now emerging, especially with through silicon via (TSV) technology. Before TSV formation by copper plating can occur, it must have a good barrier to prevent copper diffusion into silicon and also a conducting layer to enable the copper plating. Although TaN is currently the best material to use as a barrier layer, it still has several drawbacks. First, because TaN is comprised of several equilibrium phases and metastable structures, changing the atomic ratio can influence the film structure. Second, TaN-based films can only be deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods, which are high cost and require special conditions such as a vacuum and high temperatures. Furthermore, for high aspect ratio vias and trenches, PVD and CVD are unable to create a uniform conformal structure. The conducting layer is also deposited by PVD or CVD. If the seed layer coverage is not complete, the via filling process easily fails. In this situation, another process is needed to resolve this problem. To resolve these issues, cobalt-tungsten-phosphorus (CoWP) was chosen as the barrier layer. According to the previous study, CoWP film was needed in the annealing process to help remove defects. For this high temperature process, the thermal budget needed to be considered. In order to simplify the process, a method of chemical treatment was examined. This work used an overall wet process to carry out TSV metallization, using CoWP as the barrier layer and copper as the seed layer. First, the wafer was prepared with a surface pretreatment of (3-Aminopropyl)trimethoxysilane(APTMS) via silanization, follow by adsorption of Pd+2 onto the surface. These deposition points then acted as the nucleation sites for electroless deposition of CoWP. During this process, the organic additive UPS was added to modify the surface morphology of the film with only 0.1 ppm UPS, the film become denser and helped to eliminate defects. The CoWP film can effectively block copper diffusion and has good barrier ability even after annealing at 600℃ for 30 minutes. Copper nanoparticles (CNPs) were then deposited on CoWP through chemical grafting. The CNPs became the nucleation sites for copper electroless deposition. Properties such as elemental makeup, surface morphology, and thermal stability was examined and investigated by various instruments. Using this process, an aspect ratio of 6 was achieved. Wei-Ping Dow 竇維平 2011 學位論文 ; thesis 112 zh-TW |
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碩士 === 國立中興大學 === 化學工程學系所 === 99 === The development of science is constantly progressing. The densification of electronic components continuously increases. In order to meet this general demand, many new three-dimensional (3D) electronic packaging technologies are now emerging, especially with through silicon via (TSV) technology. Before TSV formation by copper plating can occur, it must have a good barrier to prevent copper diffusion into silicon and also a conducting layer to enable the copper plating. Although TaN is currently the best material to use as a barrier layer, it still has several drawbacks. First, because TaN is comprised of several equilibrium phases and metastable structures, changing the atomic ratio can influence the film structure. Second, TaN-based films can only be deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD) methods, which are high cost and require special conditions such as a vacuum and high temperatures. Furthermore, for high aspect ratio vias and trenches, PVD and CVD are unable to create a uniform conformal structure. The conducting layer is also deposited by PVD or CVD. If the seed layer coverage is not complete, the via filling process easily fails. In this situation, another process is needed to resolve this problem. To resolve these issues, cobalt-tungsten-phosphorus (CoWP) was chosen as the barrier layer. According to the previous study, CoWP film was needed in the annealing process to help remove defects. For this high temperature process, the thermal budget needed to be considered. In order to simplify the process, a method of chemical treatment was examined.
This work used an overall wet process to carry out TSV metallization, using CoWP as the barrier layer and copper as the seed layer. First, the wafer was prepared with a surface pretreatment of (3-Aminopropyl)trimethoxysilane(APTMS) via silanization, follow by adsorption of Pd+2 onto the surface. These deposition points then acted as the nucleation sites for electroless deposition of CoWP. During this process, the organic additive UPS was added to modify the surface morphology of the film with only 0.1 ppm UPS, the film become denser and helped to eliminate defects. The CoWP film can effectively block copper diffusion and has good barrier ability even after annealing at 600℃ for 30 minutes. Copper nanoparticles (CNPs) were then deposited on CoWP through chemical grafting. The CNPs became the nucleation sites for copper electroless deposition. Properties such as elemental makeup, surface morphology, and thermal stability was examined and investigated by various instruments. Using this process, an aspect ratio of 6 was achieved.
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author2 |
Wei-Ping Dow |
author_facet |
Wei-Ping Dow Chia-Pei Chou 周嘉珮 |
author |
Chia-Pei Chou 周嘉珮 |
spellingShingle |
Chia-Pei Chou 周嘉珮 Electroless Deposition of Barrier and Seed Layersof Through Silicon Via |
author_sort |
Chia-Pei Chou |
title |
Electroless Deposition of Barrier and Seed Layersof Through Silicon Via |
title_short |
Electroless Deposition of Barrier and Seed Layersof Through Silicon Via |
title_full |
Electroless Deposition of Barrier and Seed Layersof Through Silicon Via |
title_fullStr |
Electroless Deposition of Barrier and Seed Layersof Through Silicon Via |
title_full_unstemmed |
Electroless Deposition of Barrier and Seed Layersof Through Silicon Via |
title_sort |
electroless deposition of barrier and seed layersof through silicon via |
publishDate |
2011 |
url |
http://ndltd.ncl.edu.tw/handle/00998999624929322458 |
work_keys_str_mv |
AT chiapeichou electrolessdepositionofbarrierandseedlayersofthroughsiliconvia AT zhōujiāpèi electrolessdepositionofbarrierandseedlayersofthroughsiliconvia AT chiapeichou yǐwúdiàndùfǎchénjīxìtōngkǒngzhīzǔzhàngcéngyǔdǎodiàncéng AT zhōujiāpèi yǐwúdiàndùfǎchénjīxìtōngkǒngzhīzǔzhàngcéngyǔdǎodiàncéng |
_version_ |
1718556985145688064 |