SRAM with high static noide margin and low standby power consumption
碩士 === 修平技術學院 === 電機工程研究所 === 99 === This paper describes a new circuit approach for a Static Random Access Memory （SRAM）with high Static Noide Margin（SNM） and low standby power consumption comprising a memory array, a plurality of control units and a standby start-up circuit. The memory array...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/52570752519725174692 |