Improvements of poly depletion effects by TiN barrier modification on the 50nm DRAM

• Main Authors: Yi Chun Lin, 林宜君
• Other Authors: C. S. Lai
• Format: Others
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/18927362889439932993

碩士 === 長庚大學 === 電子工程學系 === 99 === In recent days, the primary gate fabrication for 0.25-um CMOS process is the dual-poly gate instead of single-poly one. Single-poly gate devices applied the buried channel for threshold-voltage adjustment. However, the depth of channel is hard to be implemented near the surface, so the devices might suffer the short channel effect. Advantages of using the dual-poly gate for PMOS devices lie in forming the device into surface- channel fabrication for controlling the short channel effect and tuning the threshold voltage easily. Unfortunately, dual-poly gate device still face some issues such as poly-depletion. Ploy-depletion will increase the total equivalent oxide thickness and decrease the gate capacitance. In this thesis, the multi-gate structure is poly-Si/TiN/WN/W. We modify the N2 concentration and thickness of the TiN diffusion barrier layer which is used to suppress the poly-depletion effect. According to the C-V curves, the depletion status are obviously improved. Besides, from the on/off ratios and curves of IDS-VGS, high drive-current and transconductance maximum can be obtained. SIMS results reveal that high Boron elements locate in the bottom of poly-Si gate which indicates the improvement.