Improvements of poly depletion effects by TiN barrier modification on the 50nm DRAM
碩士 === 長庚大學 === 電子工程學系 === 99 === In recent days, the primary gate fabrication for 0.25-um CMOS process is the dual-poly gate instead of single-poly one. Single-poly gate devices applied the buried channel for threshold-voltage adjustment. However, the depth of channel is hard to be implemented ne...
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| Format: | Others |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/18927362889439932993 |