Design of a low-power 6.44-GHz multiloop VCO with 0.18-μm CMOS technology.
碩士 === 元智大學 === 通訊工程學系 === 98 === This thesis presents the design of three-stage voltage-controlled ring oscillators. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the phase noise. We design a three-stage ring...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/38805501020899790025 |