Clock Gating Optimization with Delay-Matching Cells
碩士 === 元智大學 === 資訊工程學系 === 98 === Clock gating is an effective method of reducing power dissipation of a high-performance circuit. However, deployment of gated cells increases the difficulty of synthesizing a low-skew gated tree. In this thesis, we propose a delay-matching approach to addressing thi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45428789682951843501 |