A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES

碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog...

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Main Authors:	Pei-Hsin Chiu, 邱佩欣
Other Authors:	Shu-Chuan Huang
Format:	Others
Language:	en_US
Published:	2010
Online Access:	http://ndltd.ncl.edu.tw/handle/19521935575338319191

id	ndltd-TW-098TTU05442008
record_format	oai_dc
spelling	ndltd-TW-098TTU054420082016-04-25T04:27:13Z http://ndltd.ncl.edu.tw/handle/19521935575338319191 A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES 採用無負載及運算放大器共享技術之一伏特十位元10MSample/s低功率管線式類比數位轉換器 Pei-Hsin Chiu 邱佩欣碩士大同大學電機工程學系(所) 98 In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog converter (MDAC) is accomplished with the switched-opamp technique without any multiplied voltage circuit or low-threshold process. Furthermore, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the capacitive loading and to improve the speed in low-voltage switch circuit. As a result, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption. The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 52.92 dB with sampling frequency of 10MHz at input frequency of 0.55MHz. Power consumption of this ADC is 17.4mW with 1V power supply. Shu-Chuan Huang 黃淑絹 2010 學位論文 ; thesis 51 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog converter (MDAC) is accomplished with the switched-opamp technique without any multiplied voltage circuit or low-threshold process. Furthermore, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the capacitive loading and to improve the speed in low-voltage switch circuit. As a result, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption. The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 52.92 dB with sampling frequency of 10MHz at input frequency of 0.55MHz. Power consumption of this ADC is 17.4mW with 1V power supply.
author2	Shu-Chuan Huang
author_facet	Shu-Chuan Huang Pei-Hsin Chiu 邱佩欣
author	Pei-Hsin Chiu 邱佩欣
spellingShingle	Pei-Hsin Chiu 邱佩欣 A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
author_sort	Pei-Hsin Chiu
title	A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
title_short	A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
title_full	A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
title_fullStr	A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
title_full_unstemmed	A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
title_sort	low power, 1-v, 10-bit, 10msample/s pipelined adc with loading-free and opamp-sharing techniques
publishDate	2010
url	http://ndltd.ncl.edu.tw/handle/19521935575338319191
work_keys_str_mv	AT peihsinchiu alowpower1v10bit10msamplespipelinedadcwithloadingfreeandopampsharingtechniques AT qiūpèixīn alowpower1v10bit10msamplespipelinedadcwithloadingfreeandopampsharingtechniques AT peihsinchiu cǎiyòngwúfùzàijíyùnsuànfàngdàqìgòngxiǎngjìshùzhīyīfútèshíwèiyuán10msamplesdīgōnglǜguǎnxiànshìlèibǐshùwèizhuǎnhuànqì AT qiūpèixīn cǎiyòngwúfùzàijíyùnsuànfàngdàqìgòngxiǎngjìshùzhīyīfútèshíwèiyuán10msamplesdīgōnglǜguǎnxiànshìlèibǐshùwèizhuǎnhuànqì AT peihsinchiu lowpower1v10bit10msamplespipelinedadcwithloadingfreeandopampsharingtechniques AT qiūpèixīn lowpower1v10bit10msamplespipelinedadcwithloadingfreeandopampsharingtechniques
_version_	1718232977414029312

A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES

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