A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19521935575338319191 |