A LOW POWER, 1-V, 10-BIT, 10MSAMPLE/S PIPELINED ADC WITH LOADING-FREE AND OPAMP-SHARING TECHNIQUES
碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog...
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| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19521935575338319191 |
| Summary: | 碩士 === 大同大學 === 電機工程學系(所) === 98 === In this thesis, a 10-bit 10MHz pipelined analog-to-digital converter (ADC) consisting of 1.5-bit/stage has been designed using TSMC 0.18-μm 1P6M CMOS process models. For realizing the pipelined ADC with 1V, an innovative circuit for multiplying digital-to-analog converter (MDAC) is accomplished with the switched-opamp technique without any multiplied voltage circuit or low-threshold process. Furthermore, this thesis proposes a novel pipelined stage by combining the opamp-sharing and loading-free techniques to reduce the capacitive loading and to improve the speed in low-voltage switch circuit. As a result, the proposed pipelined ADC can operate under low power supply and reduce the total power consumption.
The ADC has been simulated by HSPICE. The resulting peak signal-to-noise and distortion ratio (SNDR) of the pipelined ADC is 52.92 dB with sampling frequency of 10MHz at input frequency of 0.55MHz. Power consumption of this ADC is 17.4mW with 1V power supply.
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