Design and Performance Evaluation of Parallel Bit-reversal with OpenMP, Cilk and UPC
碩士 === 靜宜大學 === 資訊工程學系碩士班 === 98 === Most commonly used hardware architecture was a multi-core machine, but most of the application programs were written in sequential one. In this thesis, to fully utilize the multi-core machine, we design a parallel Bit-Reversal algorithm for Fast Fourier Transfor...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/32882217516108632463 |