| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 98 === The size of semiconductor technology is reducing to 32 nm and is getting smaller. At the same time the intellectual properties (IP) cores is increasing. With the progressing of deep submicron chip technology, we can put billions of transistors on a single chip nowadays. Therefore System on Chip (SoC) designs will be able to put large numbers of IP cores on one chip. On chip communication architectures becomes an important issue in System on Chip (SoC) design in order to get a better performance. Lately Network on Chip (NoC) has been brought up to solve complex SoC communication problems and is now widely accepted by academe and industry due to its better scalability and reliability. The 2D mesh NoC has simple routing algorithm and good network scalability therefore becomes a well-liked topology of earlier NoC designs. While some packet with large distance traffic may have higher transmission latency due to the comparatively long average distance between any different two nodes in a 2D mesh. We propose a simple design method for 2D mesh NoC called Star Type architecture in this thesis. The basic concept is to let the packets with large distance traffic travel on an extra second level mesh. The experiment environment is using a 12 × 12 Star Type NoC, which is divided by 3 × 3 sub-mesh. We use the ORION 2.0 power and area model to simulate. Simulation results demonstrate that it can reduce the hops traversed for long distance traffic. And the product of area, power and hop counts of Star Type 12 × 12 mesh can be decreased by 17.2%, and 10.3% compared to normal mesh architectures and 2-Level mesh, respectively.
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