A Low Transmission Latency Method of Star Type Architecture Based on 2D Mesh NOC
碩士 === 國立臺灣大學 === 電機工程學研究所 === 98 === The size of semiconductor technology is reducing to 32 nm and is getting smaller. At the same time the intellectual properties (IP) cores is increasing. With the progressing of deep submicron chip technology, we can put billions of transistors on a single chip n...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2009
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| Online Access: | http://ndltd.ncl.edu.tw/handle/48641168568972686158 |