VLSI Interconnect Delay and Slew Metrics Using Probability Distribution

博士 === 臺灣大學 === 電機工程學研究所 === 98 === As integrated circuit process technology is changing into the ultra deep submicron era, the complex interconnection topology and metal resistance shielding effects problems are very serious, resulting in very stiff interconnection structure. As inaccurate delay on...

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Bibliographic Details
Main Authors:	Jun-Kuei Zeng, 曾俊貴
Other Authors:	陳中平
Format:	Others
Language:	en_US
Published:	2010
Online Access:	http://ndltd.ncl.edu.tw/handle/14476069157913153510

id	ndltd-TW-098NTU05442015
record_format	oai_dc
spelling	ndltd-TW-098NTU054420152015-10-13T13:40:20Z http://ndltd.ncl.edu.tw/handle/14476069157913153510 VLSI Interconnect Delay and Slew Metrics Using Probability Distribution 應用機率分佈快速準確計算超大型積體電路導線延遲及斜率 Jun-Kuei Zeng 曾俊貴博士臺灣大學電機工程學研究所 98 As integrated circuit process technology is changing into the ultra deep submicron era, the complex interconnection topology and metal resistance shielding effects problems are very serious, resulting in very stiff interconnection structure. As inaccurate delay on stiff interconnect sinks creates a situation where decisions on when to evaluate by statistical static time analysis are not cluster distribution, we cannot roughly classify the interconnect into near-end, middle-end, and far-end. Although several delay metrics have been proposed, they are inefficient and difficult to implement. Hence, we propose several new delay metrics for interconnection based on probability distribution. Our metrics are efficient, easy to implement, and can precisely label inaccurate sinks and efficiently calibrate them; the overall standard deviation and error mean are smaller than in previous works. 陳中平 2010 學位論文 ; thesis 84 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	博士 === 臺灣大學 === 電機工程學研究所 === 98 === As integrated circuit process technology is changing into the ultra deep submicron era, the complex interconnection topology and metal resistance shielding effects problems are very serious, resulting in very stiff interconnection structure. As inaccurate delay on stiff interconnect sinks creates a situation where decisions on when to evaluate by statistical static time analysis are not cluster distribution, we cannot roughly classify the interconnect into near-end, middle-end, and far-end. Although several delay metrics have been proposed, they are inefficient and difficult to implement. Hence, we propose several new delay metrics for interconnection based on probability distribution. Our metrics are efficient, easy to implement, and can precisely label inaccurate sinks and efficiently calibrate them; the overall standard deviation and error mean are smaller than in previous works.
author2	陳中平
author_facet	陳中平 Jun-Kuei Zeng 曾俊貴
author	Jun-Kuei Zeng 曾俊貴
spellingShingle	Jun-Kuei Zeng 曾俊貴 VLSI Interconnect Delay and Slew Metrics Using Probability Distribution
author_sort	Jun-Kuei Zeng
title	VLSI Interconnect Delay and Slew Metrics Using Probability Distribution
title_short	VLSI Interconnect Delay and Slew Metrics Using Probability Distribution
title_full	VLSI Interconnect Delay and Slew Metrics Using Probability Distribution
title_fullStr	VLSI Interconnect Delay and Slew Metrics Using Probability Distribution
title_full_unstemmed	VLSI Interconnect Delay and Slew Metrics Using Probability Distribution
title_sort	vlsi interconnect delay and slew metrics using probability distribution
publishDate	2010
url	http://ndltd.ncl.edu.tw/handle/14476069157913153510
work_keys_str_mv	AT junkueizeng vlsiinterconnectdelayandslewmetricsusingprobabilitydistribution AT céngjùnguì vlsiinterconnectdelayandslewmetricsusingprobabilitydistribution AT junkueizeng yīngyòngjīlǜfēnbùkuàisùzhǔnquèjìsuànchāodàxíngjītǐdiànlùdǎoxiànyánchíjíxiélǜ AT céngjùnguì yīngyòngjīlǜfēnbùkuàisùzhǔnquèjìsuànchāodàxíngjītǐdiànlùdǎoxiànyánchíjíxiélǜ
_version_	1717740694903193600

VLSI Interconnect Delay and Slew Metrics Using Probability Distribution

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