VLSI Interconnect Delay and Slew Metrics Using Probability Distribution
博士 === 臺灣大學 === 電機工程學研究所 === 98 === As integrated circuit process technology is changing into the ultra deep submicron era, the complex interconnection topology and metal resistance shielding effects problems are very serious, resulting in very stiff interconnection structure. As inaccurate delay on...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/14476069157913153510 |