| Summary: | 博士 === 臺灣大學 === 電機工程學研究所 === 98 === As integrated circuit process technology is changing into the ultra deep submicron era, the complex interconnection topology and metal resistance shielding effects problems are very serious, resulting in very stiff interconnection structure. As inaccurate delay on stiff interconnect sinks creates a situation where decisions on when to evaluate by statistical static time analysis are not cluster distribution, we cannot roughly classify the interconnect into near-end, middle-end, and far-end. Although several delay metrics have been proposed, they are inefficient and difficult to implement. Hence, we propose several new delay metrics for interconnection based on probability distribution. Our metrics are efficient, easy to implement, and can precisely label inaccurate sinks and efficiently calibrate them; the overall standard deviation and error mean are smaller than in previous works.
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